排列三跨度走势图近10o期

Single Wire Aggregation

PCB congestion relief using FPGAs for signal aggregation and transmission over single wire

PCB design challenges – In many systems processors use multiple interfaces including I2C, GPIO, I2S and UART to collect data from peripherals and sensors. In some of these systems PCB real estate is a premium in addition designers are going with smaller PCBs that connect together to fit into neat looking industrial designs. Routing signals through congested PCBs and connectors presents some challenges.

FPGA based solution – The Single wire Aggregation reference design runs on two iCE40 UltraPlus FPGAs to aggregate multiple data streams such as I2C, UART, I2S and GPIO in TDM fashion by one FPGA and send it over a single wire to the other FPGA for de-aggregation back to the same set of streams.

Flexible & robust options – The single wire communication between the FPGAs is around 7.5 Mbps. The design is also configurable, the number of I2C/I2S busses and GPIOs and single wire protocol packet length can be adjusted. The single wire protocol between the FPGA is robust with error detection and retry features.

Features

  • Up to 7 channels can be aggregated
  • Raw data rate on single wire is ∼7.5 Mbps or higher
  • Variable packet length for efficient use of the single wire bandwidth
  • Retransmit feature is offered when parity error is detected on RX side
  • Supports I2C Fast-mode (400 kbps) and Fast-mode Plus (1 Mbps)
  • I2C Interrupt can be realized by GPIO with event-based transmission
  • I2S supports single stereo channel, 48K hz sampling rate, up to 32 bits per sample with bi-directional support

Block Diagram

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Single Wire Aggregation Radiant - Source Code
1.1 9/28/2018 ZIP 2 MB
Single Wire Signal Aggregation - Documentation
FPGA-RD-02039 1.1 9/28/2018 PDF 999 KB


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排列三跨度走势图近10o期
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